For example, the I2C communication (called ‘I-squared-C’; that is an abbreviation of ‘Inter-Integrated Circuit’) is known as data communication to be carried out by a master device and a slave device by way of two types of signal lines, namely a serial clock line and a serial data line, wherein bus specifications of the I2C communication being proposed and put into practical use by Philips.
Meanwhile, ICs such as an EEPROM, accessible by way of the I2C communication, are widely produced and on the market. ICs according to the I2C communication standards are called I2C devices.
Known is a device having a structure in which a single master device and a plurality of slave devices are connected by using a serial clock line and a serial data line, as an I2C device (for example, refer to FIG. 5 of Patent Document 1). A potential of the serial clock line and the serial data line is pulled up to a power-supply voltage via resistor. All signals including a data signal and a clock signal are arbitrarily generated by decreasing the high-leveled signal line level down to a low level.
In the I2C communication, information of a command, a datum, and the like is transmitted from the master device to the slave devices by the byte (8 bits). Moreover, an address is transmitted, for example, by using either 7 bits or 10 bits.
While one-byte information is transmitted from the master device to a slave device, the slave device having received the information returns an acknowledge signal attached to each byte. Then, the master device having received the acknowledge signal transmits a next byte. A series of operations described above are repeated until an end of communication.
In the I2C communication, the master device controls all of a start & end of communication, an address assignment, a direction of data sending/receiving (to control writing/reading data, in the view from the master device side), generating an acknowledge signal, and generating & sending a clock signal.
In this regard, a slave device is provided with a right for the slave device itself not to return the acknowledge signal, or to forcibly lower a signal level of the serial clock line in the case where the slave device becomes unable to receive a data byte, or it is desired to delay data receiving by way of internal processing.
Thus, a system in the I2C communication is standardized in such a way that a slave device can receive information without any incorrect operation during a data receiving operation.
Patent Document 1: Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2006-090473
Unfortunately, I2C does not specify any arrangement for protection against incorrect operation caused due to an initialization processing operation in the case where it becomes necessary to return a slave device into an initial condition, either after a master device resets the slave device, or after turning on the power supply.
Therefore, after resetting the slave device by some means, the master device has no way of checking whether or not the I2C device is ready for communication.
Accordingly, after the resetting, the master device has no other way but accesses the slave device after spending a certain time period.
In the case of accessing the slave device without spending the certain time period described above after the master device sends a resetting signal, appropriate accessing cannot be implemented so that the slave device may malfunction. A minimum required time for the certain time period described above varies, depending on a circuit configuration. Therefore, a latency time in order to resume the slave device must be set according to an actual measured value, unfortunately after building an actual system. Moreover, the certain time period described above is set by way of adding a margin to the minimum required time in order to protect against incorrect operation, and therefore, it is impossible to prevent a useless latency time from coming up.